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Browsing by Subject "10T-SRAM"

Browsing by Subject "10T-SRAM"

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  • Joshi R.V.; Kanj R.; Saroop S. (Institute of Electrical and Electronics Engineers Inc.; PISCATAWAY445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA, 2014)
    Novel 9T-8T SRAM cell designs are demonstrated using a fully functional 75-kb L1-cache compatible interleaved hardware based design in 45 nm SOI. An integrated read stack, together with an asymmetrical precharge topology, ...

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