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Instruction-set extension for cryptographic applications on reconfigurable platform

Show simple item record Majzoub S. Diab H.
dc.contributor.editor 2007 2017-09-07T07:07:17Z 2017-09-07T07:07:17Z 2007
dc.identifier 10.1142/S0218126607004076
dc.identifier.issn 02181266
dc.description.abstract Reconfigurable Systems represent a middle trade-off between speed and flexibility in the processor design world. It provides performance close to the custom-hardware and yet preserves some of the general-purpose processor flexibility. Recently, the area of reconfigurable computing has received considerable interest in both its forms: the FPGA and coarse-grain hardware. Since the field is still in its developing stage, it is important to perform hardware analysis and evaluation of certain key applications on target reconfigurable architectures to identify potential limitations and improvements. This paper presents the mapping and performance analysis of two encryption algorithms, namely Rijndael and Twofish, on a coarse grain reconfigurable platform, namely MorphoSys. MorphoSys is a reconfigurable architecture targeted for multimedia applications. Since many cryptographic algorithms involve bitwise operations, bitwise instruction set extension was proposed to enhance the performance. We present the details of the mapping of the bitwise operations involved in the algorithms with thorough analysis. The methodology we used can be utilized in other systems. © 2007 World Scientific Publishing Company.
dc.format.extent Pages: (911-927)
dc.language English
dc.publisher SINGAPORE
dc.relation.ispartof Publication Name: Journal of Circuits, Systems and Computers; Publication Year: 2007; Volume: 16; no. 6; Pages: (911-927);
dc.source Scopus
dc.title Instruction-set extension for cryptographic applications on reconfigurable platform
dc.type Article
dc.contributor.affiliation Majzoub, S., Faculty of Engineering and Architecture, American University of Beirut, P. O. Box 11-0236 Riad El Solh, Beirut 1107 2020, Lebanon
dc.contributor.affiliation Diab, H., Faculty of Engineering and Architecture, American University of Beirut, P. O. Box 11-0236 Riad El Solh, Beirut 1107 2020, Lebanon
dc.contributor.authorAddress Majzoub, S.; Faculty of Engineering and Architecture, American University of Beirut, P. O. Box 11-0236 Riad El Solh, Beirut 1107 2020, Lebanon; email:
dc.contributor.authorCorporate University: American University of Beirut; Faculty: Faculty of Engineering and Architecture; Department: Electrical and Computer Engineering;
dc.contributor.authorDepartment Electrical and Computer Engineering
dc.contributor.authorFaculty Faculty of Engineering and Architecture
dc.contributor.authorInitials Majzoub, S
dc.contributor.authorInitials Diab, H
dc.contributor.authorReprintAddress Majzoub, S (reprint author), Amer Univ Beirut, Fac Engn and Architecture, POB 11-0236 Riad El Solh, Beirut 11072020, Lebanon.
dc.contributor.authorUniversity American University of Beirut
dc.description.cited Al-Khalidy M, 2004, INT C CURR ISS BUS I; Almaini AEA, 1994, ELECT LOGIC SYSTEMS; Daemen J., 2002, DESIGN RIJNDAEL AES; Diab H, 2003, ACS IEEE INT C COMP; Green D.H., 1986, MODERN LOGIC DESIGN; HARTENSTEIN R, 2001, P C AS S PAC DES AUT; HARTENSTEIN R, 2001, DECADE RECONFIGURABL; HAUCK S, 1998, CAN C FIELD PROGR DE; HAUSER J, 1997, P IEEE FCCM 97 NAP C; *IST PROGR, ARCH METH DYN REC LO; Itani M, 2004, IEEE ACS INT C PERV; KOZYRAKIS CE, 1998, IEEE COMPUT, V31, P24; Lee MH, 2000, J VLSI SIG PROCESS S, V24, P147, DOI 10.1023-A:1008189221436; Majzoub S, 2003, ACS IEEE INT C COMP; MAJZOUB S, IEEE S SIGN PROC INF; Mei B., 2003, FIELD PROGRAMMABLE L; MIRSKY E, 1996, P IEEE FCCM 96 NAPA; MIYAMORI T, 1998, P ACM SIGDA FPGA 98; Schneier B., 1996, APPL CRYPTOGRAPHY PR; Schneier B., 1998, TWOFISH 128 BIT BLOC; Singh H, 2000, IEEE T COMPUT, V49, P465, DOI 10.1109-12.859540; TESSIER R, 2002, PROGRAMMABLE DIGITAL; Yeary AB, 2004, IEEE T INSTRUM MEAS, V53, P665, DOI 10.1109-TIM.2004.827095
dc.description.citedTotWOSCount 0
dc.description.citedWOSCount 0
dc.format.extentCount 17
dc.identifier.coden JCSME
dc.identifier.scopusID 44349098271
dc.publisher.address 5 TOH TUCK LINK, SINGAPORE 596224, SINGAPORE
dc.relation.ispartOfISOAbbr J. Circuits Syst. Comput.
dc.relation.ispartOfIssue 6
dc.relation.ispartofPubTitle Journal of Circuits, Systems and Computers
dc.relation.ispartofPubTitleAbbr J. Circuits Syst. Comput.
dc.relation.ispartOfVolume 16
dc.source.ID WOS:000256095700005
dc.type.publication Journal
dc.subject.otherAuthKeyword Compiler
dc.subject.otherAuthKeyword MorphoSys
dc.subject.otherAuthKeyword Reconfigurable hardware
dc.subject.otherAuthKeyword Rijndael
dc.subject.otherAuthKeyword Twofish
dc.subject.otherIndex Algorithms
dc.subject.otherIndex Program compilers
dc.subject.otherIndex Systems analysis
dc.subject.otherIndex MorphoSys
dc.subject.otherIndex Reconfigurable hardware
dc.subject.otherIndex Cryptography
dc.subject.otherKeywordPlus MORPHOSYS
dc.subject.otherWOS Computer Science, Hardware and Architecture
dc.subject.otherWOS Engineering, Electrical and Electronic

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