Abstract:
A low power SRAM macro is customized in 90nm TSMC model technology. The design minimizes the area of the bitcells to achieve a total area of 0.370 mm 2. A dynamic supply voltage management scheme is used to reduce the leakage power in the standby mode. The 64 kbits sub-array operates at 1.54 GHz for 1.0V supply voltage. Monte carlo simulation results show that the macro has a 6percent failure probability under Vt process variations. ©2010 IEEE.