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A 640-Mb-s 2048-bit programmable LDPC decoder chip

Show simple item record Mansour M.M. Shanbhag N.R.
dc.contributor.editor 2006 2017-09-07T07:08:35Z 2017-09-07T07:08:35Z 2006
dc.identifier 10.1109/JSSC.2005.864133
dc.identifier.issn 00189200
dc.description.abstract A 14.3-mm 2 code-programmable and code-rate tunable decoder chip for 2048-bit low-density parity-check (LDPC) codes is presented. The chip implements the turbo-decoding message-passing (TDMP) algorithm for architecture-aware (AA-)LDPC codes which has a faster convergence rate and hence a throughput advantage over the standard decoding algorithm. It employs a reduced complexity message computation mechanism free of lookup tables, and features a programmable network for message interleaving based on the code structure. The chip decodes any mix of 2048-bit rate-1-2 (3,6)-regular AA-LDPC codes in standard mode by programming the network, and attains a throughput of 640 Mb-s at 125 MHz for 10 TDMP-decoding iterations. In augmented mode, the code rate can be tuned up to 14-16 in steps of 1-16 by augmenting the code. The chip is fabricated in 0.18-μm six-metal-layer CMOS technology, operates at a peak clock frequency of 125 MHz at 1.8 V (nominal), and dissipates an average power of 787 mW. © 2006 IEEE.
dc.format.extent Pages: (684-697)
dc.language English
dc.publisher PISCATAWAY
dc.relation.ispartof Publication Name: IEEE Journal of Solid-State Circuits; Publication Year: 2006; Volume: 41; no. 3; Pages: (684-697);
dc.source Scopus
dc.title A 640-Mb-s 2048-bit programmable LDPC decoder chip
dc.type Article
dc.contributor.affiliation Mansour, M.M., IEEE, Lebanon, Department of Electrical and Computer Engineering, American University of Beirut, Beirut 1107 2020, Lebanon, Department of Electrical and Computer Engineering, AUB, Lebanon
dc.contributor.affiliation Shanbhag, N.R., IEEE, Lebanon, Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL 61801, United States, Department of Electrical and Computer Engineering, Coordinated Science Laboratory, University of Illinois, Urbana-Champaign, United States, Illinois Center for Integrated Microsystems, University of Illinois, United States, VLSI Information Processing Systems (ViPS) Group, United States
dc.contributor.authorAddress Mansour, M.M.; Department of Electrical and Computer Engineering, American University of Beirut, Beirut 1107 2020, Lebanon; email:
dc.contributor.authorCorporate University: American University of Beirut; Faculty: Faculty of Engineering and Architecture; Department: Electrical and Computer Engineering;
dc.contributor.authorDepartment Electrical and Computer Engineering
dc.contributor.authorFaculty Faculty of Engineering and Architecture
dc.contributor.authorInitials Mansour, MM
dc.contributor.authorInitials Shanbhag, NR
dc.contributor.authorReprintAddress Mansour, MM (reprint author), Amer Univ Beirut, Dept Elect and Comp Engn, Beirut 1107 2020, Lebanon.
dc.contributor.authorUniversity American University of Beirut
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dc.description.citedCount 132
dc.description.citedTotWOSCount 95
dc.description.citedWOSCount 88
dc.format.extentCount 14
dc.identifier.coden IJSCB
dc.identifier.scopusID 33644640388
dc.publisher.address 445 HOES LANE, PISCATAWAY, NJ 08855 USA
dc.relation.ispartOfISOAbbr IEEE J. Solid-State Circuit
dc.relation.ispartOfIssue 3
dc.relation.ispartofPubTitle IEEE Journal of Solid-State Circuits
dc.relation.ispartofPubTitleAbbr IEEE J Solid State Circuits
dc.relation.ispartOfVolume 41
dc.source.ID WOS:000235764000016
dc.type.publication Journal
dc.subject.otherAuthKeyword Architecture-aware low-density parity-check (AA-LDPC) codes
dc.subject.otherAuthKeyword Iterative decoders
dc.subject.otherAuthKeyword LDPC codes
dc.subject.otherAuthKeyword Turbodecoding message-passing (TDMP) algorithm
dc.subject.otherAuthKeyword VLSI decoder architectures
dc.subject.otherIndex Architecture-aware low-density parity-check (AA-LDPC) codes
dc.subject.otherIndex Iterative decoders
dc.subject.otherIndex LDPC codes
dc.subject.otherIndex Turbodecoding message-passing (TDMP) algorithm
dc.subject.otherIndex VLSI decoder architectures
dc.subject.otherIndex Algorithms
dc.subject.otherIndex CMOS integrated circuits
dc.subject.otherIndex Computation theory
dc.subject.otherIndex Convergence of numerical methods
dc.subject.otherIndex Decoding
dc.subject.otherIndex Iterative methods
dc.subject.otherIndex Table lookup
dc.subject.otherIndex Microprocessor chips
dc.subject.otherKeywordPlus PARITY-CHECK CODES
dc.subject.otherKeywordPlus RECORDING CHANNELS
dc.subject.otherWOS Engineering, Electrical and Electronic

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