Abstract:
A low power SRAM macro is designed in 90nm TSMC model technology. The design is customized with Cadence Environment for minimal bit cell area, resulting in an area of 0.370 mm 2. To reduce leakage power in standby mode, the SRAM architecture employs a dynamic supply voltage management scheme. The 64 kbits sub-array can run at 1.54 GHz at 1.0V supply voltage. Results demonstrated that the macro has a 6percent failure probability when tested for threshold voltage process variation. © 2009 IEEE.