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A fast recursive algorithm and architecture for pruned bit-reversal interleavers

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dc.contributor.author Mansour M.M.
dc.contributor.editor
dc.date 2013
dc.date.accessioned 2017-10-04T11:07:17Z
dc.date.available 2017-10-04T11:07:17Z
dc.date.issued 2013
dc.identifier 10.1007/s11265-012-0721-3
dc.identifier.isbn
dc.identifier.issn 19398018
dc.identifier.uri http://hdl.handle.net/10938/14481
dc.description.abstract In this paper, pruned bit-reversal permutations employed in variable-length interleavers and their associated fast pruning algorithms and architectures are considered. Pruning permutations is mathematically formulated as a counting problem in a set of k integers and any subset of α consecutive integers under some permutation, where integers from this subset that map into indices less than some β k are to be counted. A solution to this problem using sums involving integer floors and related functions is proposed. It is shown that these sums can be evaluated recursively using integer operations. Specifically, a mathematical treatment for bit-reversal permutations (BRPs) and their permutation statistics are presented. These permutations have been mainly addressed using numerical techniques in the literature to speed up in-place computations of fast Fourier and related transforms. Closed-form expressions for BRP statistics including inversions, serial correlations, and a new statistic called permutation inliers that characterizes the pruning gap of pruned interleavers, are derived. Using the inliers statistic, a recursive algorithm that computes the minimum number of inliers in a pruned BR interleaver (PBRI) in logarithmic time complexity is presented. This algorithm enables parallelizing a serial PBRI algorithm by any desired parallelism factor by computing the pruning gap in lookahead rather than a serial fashion, resulting in significant reduction in interleaving latency and memory overhead. Extensions to 2-D block and stream interleavers are also presented. Moreover, efficient hardware architectures for the proposed algorithms employing simple logic gates are presented. Simulation results of interleavers employed in modern communication standards demonstrate 3 to 4 orders of magnitude improvement in interleaving time compared to existing approaches. © 2013 Springer Science+Business Media New York.
dc.format.extent
dc.format.extent Pages: (201-219)
dc.language English
dc.publisher NEW YORK
dc.relation.ispartof Publication Name: Journal of Signal Processing Systems; Publication Year: 2013; Volume: 71; no. 3; Pages: (201-219);
dc.relation.ispartofseries
dc.relation.uri
dc.source Scopus
dc.subject.other
dc.title A fast recursive algorithm and architecture for pruned bit-reversal interleavers
dc.type Article
dc.contributor.affiliation Mansour, M.M., ECE Department, American University of Beirut, Beirut, Lebanon
dc.contributor.authorAddress Mansour, M.M.; ECE Department, American University of Beirut, Beirut, Lebanon; email: mmansour@aub.edu.lb
dc.contributor.authorCorporate University: American University of Beirut; Faculty: Faculty of Engineering and Architecture; Department: Electrical and Computer Engineering;
dc.contributor.authorDepartment Electrical and Computer Engineering
dc.contributor.authorDivision
dc.contributor.authorEmail mmansour@aub.edu.lb
dc.contributor.authorFaculty Faculty of Engineering and Architecture
dc.contributor.authorInitials Mansour, MM
dc.contributor.authorOrcidID
dc.contributor.authorReprintAddress Mansour, MM (reprint author), Amer Univ Beirut, ECE Dept, Beirut, Lebanon.
dc.contributor.authorResearcherID
dc.contributor.authorUniversity American University of Beirut
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dc.description.citedTotWOSCount 0
dc.description.citedWOSCount 0
dc.format.extentCount 19
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dc.identifier.pubmedID
dc.identifier.scopusID 84879696497
dc.identifier.url
dc.publisher.address 233 SPRING ST, NEW YORK, NY 10013 USA
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dc.relation.ispartofConferenceHosting
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dc.relation.ispartOfISOAbbr J. Signal Process. Syst. Signal Image Video Technol.
dc.relation.ispartOfIssue 3
dc.relation.ispartOfPart
dc.relation.ispartofPubTitle Journal of Signal Processing Systems
dc.relation.ispartofPubTitleAbbr J. Signal Process Syst.
dc.relation.ispartOfSpecialIssue
dc.relation.ispartOfSuppl
dc.relation.ispartOfVolume 71
dc.source.ID WOS:000316745200004
dc.type.publication Journal
dc.subject.otherAuthKeyword Bit-reversal permutations
dc.subject.otherAuthKeyword Permutation statistics
dc.subject.otherAuthKeyword Pruned interleavers
dc.subject.otherAuthKeyword Turbo interleavers
dc.subject.otherChemCAS
dc.subject.otherIndex Bit-reversal permutations
dc.subject.otherIndex Closed-form expression
dc.subject.otherIndex Communication standards
dc.subject.otherIndex Fast recursive algorithms
dc.subject.otherIndex Interleavers
dc.subject.otherIndex Mathematical treatments
dc.subject.otherIndex Permutation statistic
dc.subject.otherIndex Pruned interleavers
dc.subject.otherIndex Algorithms
dc.subject.otherIndex Computational complexity
dc.subject.otherIndex Fast Fourier transforms
dc.subject.otherIndex Statistics
dc.subject.otherIndex Turbo codes
dc.subject.otherKeywordPlus TURBO CODES
dc.subject.otherKeywordPlus PERMUTATION ALGORITHM
dc.subject.otherKeywordPlus FFT
dc.subject.otherKeywordPlus CHANNEL
dc.subject.otherKeywordPlus FOURIER
dc.subject.otherKeywordPlus DESIGN
dc.subject.otherWOS Computer Science, Information Systems
dc.subject.otherWOS Engineering, Electrical and Electronic


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