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A 640-Mb-s 2048-bit programmable LDPC decoder chip

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dc.contributor.author Mansour M.M.
dc.contributor.author Shanbhag N.R.
dc.contributor.editor
dc.date 2006
dc.date.accessioned 2017-10-04T11:07:33Z
dc.date.available 2017-10-04T11:07:33Z
dc.date.issued 2006
dc.identifier 10.1109/JSSC.2005.864133
dc.identifier.isbn
dc.identifier.issn 00189200
dc.identifier.uri http://hdl.handle.net/10938/14692
dc.description.abstract A 14.3-mm 2 code-programmable and code-rate tunable decoder chip for 2048-bit low-density parity-check (LDPC) codes is presented. The chip implements the turbo-decoding message-passing (TDMP) algorithm for architecture-aware (AA-)LDPC codes which has a faster convergence rate and hence a throughput advantage over the standard decoding algorithm. It employs a reduced complexity message computation mechanism free of lookup tables, and features a programmable network for message interleaving based on the code structure. The chip decodes any mix of 2048-bit rate-1-2 (3,6)-regular AA-LDPC codes in standard mode by programming the network, and attains a throughput of 640 Mb-s at 125 MHz for 10 TDMP-decoding iterations. In augmented mode, the code rate can be tuned up to 14-16 in steps of 1-16 by augmenting the code. The chip is fabricated in 0.18-μm six-metal-layer CMOS technology, operates at a peak clock frequency of 125 MHz at 1.8 V (nominal), and dissipates an average power of 787 mW. © 2006 IEEE.
dc.format.extent
dc.format.extent Pages: (684-697)
dc.language English
dc.publisher PISCATAWAY
dc.relation.ispartof Publication Name: IEEE Journal of Solid-State Circuits; Publication Year: 2006; Volume: 41; no. 3; Pages: (684-697);
dc.relation.ispartofseries
dc.relation.uri
dc.source Scopus
dc.subject.other
dc.title A 640-Mb-s 2048-bit programmable LDPC decoder chip
dc.type Article
dc.contributor.affiliation Mansour, M.M., IEEE, Lebanon, Department of Electrical and Computer Engineering, American University of Beirut, Beirut 1107 2020, Lebanon, Department of Electrical and Computer Engineering, AUB, Lebanon
dc.contributor.affiliation Shanbhag, N.R., IEEE, Lebanon, Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL 61801, United States, Department of Electrical and Computer Engineering, Coordinated Science Laboratory, University of Illinois, Urbana-Champaign, United States, Illinois Center for Integrated Microsystems, University of Illinois, United States, VLSI Information Processing Systems (ViPS) Group, United States
dc.contributor.authorAddress Mansour, M.M.; Department of Electrical and Computer Engineering, American University of Beirut, Beirut 1107 2020, Lebanon; email: mmansour@aub.edu.lb
dc.contributor.authorCorporate University: American University of Beirut; Faculty: Faculty of Engineering and Architecture; Department: Electrical and Computer Engineering;
dc.contributor.authorDepartment Electrical and Computer Engineering
dc.contributor.authorDivision
dc.contributor.authorEmail mmansour@aub.edu.lb; shanbhag@uiuc.edu
dc.contributor.authorFaculty Faculty of Engineering and Architecture
dc.contributor.authorInitials Mansour, MM
dc.contributor.authorInitials Shanbhag, NR
dc.contributor.authorOrcidID
dc.contributor.authorReprintAddress Mansour, MM (reprint author), Amer Univ Beirut, Dept Elect and Comp Engn, Beirut 1107 2020, Lebanon.
dc.contributor.authorResearcherID
dc.contributor.authorUniversity American University of Beirut
dc.description.cited Bangerter B., 2003, INTEL TECHNOL J, V7; BERROU C, 1993, IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS 93 : TECHNICAL PROGRAM, CONFERENCE RECORD, VOLS 1-3, P1064, DOI 10.1109-ICC.1993.397441; BIKERSTAFF M, 2003, IEEE INT SOL STAT CI, P150; BOUGARD M, 2003, IEEE INT SOL STAT CI, P152; CHEN Y, 2003, P IEEE GLOB 2003 SAN, P113; FAN J, 80220 IEEE; Gallager R., 1963, LOW DENSITY PARITY C; Howland CJ, 2001, P 2001 IEEE INT S CI, P742; Mackay DJC, 2000, CODES SYSTEMS GRAPHI, V123, P113; Mansour M. M., 2002, P INT S LOW POW EL D, P284; MANSOUR MM, 2002, P IEEE GLOB TEL C 20, P1383; Mansor M, 2003, PASOH: ECOLOGY OF A LOWLAND RAIN FOREST IN SOUTHEAST ASIA, P215; Mansour MM, 2003, IEEE T VLSI SYST, V11, P976, DOI 10.1109-TVLSI.2003.817545; MANSOUR MM, 2003, P IEEE INT S CIRC SY, V2, P57; MANSOUR MM, 2003, P IEEE WORKSHOP AUG, P159; Mansour M. M., 2003, Proceedings Fourth International Symposium on Quality Electronic Design; RASHI Y, 80215 IEEE WPAN; Richardson TJ, 2001, IEEE T INFORM THEORY, V47, P619, DOI 10.1109-18.910578; Song HW, 2002, JPN J APPL PHYS 1, V41, P1749, DOI 10.1143-JJAP.41.1749; TANNER RM, 1981, IEEE T INFORM THEORY, V27, P533, DOI 10.1109-TIT.1981.1056404; Vasic B, 2003, J LIGHTWAVE TECHNOL, V21, P438, DOI 10.1109-JLT.2003.808769; Yeo E, 2001, IEEE T MAGN, V37, P748
dc.description.citedCount 132
dc.description.citedTotWOSCount 95
dc.description.citedWOSCount 88
dc.format.extentCount 14
dc.identifier.articleNo
dc.identifier.coden IJSCB
dc.identifier.pubmedID
dc.identifier.scopusID 33644640388
dc.identifier.url
dc.publisher.address 445 HOES LANE, PISCATAWAY, NJ 08855 USA
dc.relation.ispartofConference
dc.relation.ispartofConferenceCode
dc.relation.ispartofConferenceDate
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dc.relation.ispartofConferenceSponsor
dc.relation.ispartofConferenceTitle
dc.relation.ispartofFundingAgency
dc.relation.ispartOfISOAbbr IEEE J. Solid-State Circuit
dc.relation.ispartOfIssue 3
dc.relation.ispartOfPart
dc.relation.ispartofPubTitle IEEE Journal of Solid-State Circuits
dc.relation.ispartofPubTitleAbbr IEEE J Solid State Circuits
dc.relation.ispartOfSpecialIssue
dc.relation.ispartOfSuppl
dc.relation.ispartOfVolume 41
dc.source.ID WOS:000235764000016
dc.type.publication Journal
dc.subject.otherAuthKeyword Architecture-aware low-density parity-check (AA-LDPC) codes
dc.subject.otherAuthKeyword Iterative decoders
dc.subject.otherAuthKeyword LDPC codes
dc.subject.otherAuthKeyword Turbodecoding message-passing (TDMP) algorithm
dc.subject.otherAuthKeyword VLSI decoder architectures
dc.subject.otherChemCAS
dc.subject.otherIndex Architecture-aware low-density parity-check (AA-LDPC) codes
dc.subject.otherIndex Iterative decoders
dc.subject.otherIndex LDPC codes
dc.subject.otherIndex Turbodecoding message-passing (TDMP) algorithm
dc.subject.otherIndex VLSI decoder architectures
dc.subject.otherIndex Algorithms
dc.subject.otherIndex CMOS integrated circuits
dc.subject.otherIndex Computation theory
dc.subject.otherIndex Convergence of numerical methods
dc.subject.otherIndex Decoding
dc.subject.otherIndex Iterative methods
dc.subject.otherIndex Table lookup
dc.subject.otherIndex Microprocessor chips
dc.subject.otherKeywordPlus PARITY-CHECK CODES
dc.subject.otherKeywordPlus RECORDING CHANNELS
dc.subject.otherWOS Engineering, Electrical and Electronic


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