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Scaling of i DDT test methods for random logic circuits

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dc.contributor.author Chehab A.
dc.contributor.author Patel S.
dc.contributor.author Makki R.
dc.contributor.editor
dc.date 2006
dc.date.accessioned 2017-10-04T11:07:33Z
dc.date.available 2017-10-04T11:07:33Z
dc.date.issued 2006
dc.identifier 10.1007/s10836-006-4835-z
dc.identifier.isbn
dc.identifier.issn 09238174
dc.identifier.uri http://hdl.handle.net/10938/14697
dc.description.abstract We present a scaling methodology to improve i DDT fault coverage in random logic circuits. The study targets two i DDT test methods: Double Threshold i DDT and Delayed i DDT. The effectiveness of the scaling methodology is assessed through physical test measurements, and studied relative to process variation and impact on circuit performance. The scaling is made possible using a clustering methodology that can significantly improve fault coverage. The results show that without clustering, the effectiveness of the i DDT testing methods considered is greatly reduced as the circuit size increases. © 2006 Springer Science + Business Media, Inc.
dc.format.extent
dc.format.extent Pages: (11-22)
dc.language English
dc.publisher DORDRECHT
dc.relation.ispartof Publication Name: Journal of Electronic Testing: Theory and Applications (JETTA); Publication Year: 2006; Volume: 22; no. 1; Pages: (11-22);
dc.relation.ispartofseries
dc.relation.uri
dc.source Scopus
dc.subject.other
dc.title Scaling of i DDT test methods for random logic circuits
dc.type Article
dc.contributor.affiliation Chehab, A., American University of Beirut, Beirut, Lebanon, ECE Department, AUB, Lebanon
dc.contributor.affiliation Patel, S., University of North Carolina at Charlotte, Charlotte, NC 28223, United States
dc.contributor.affiliation Makki, R., College of Information Technology, UAE University, AL-Ain, United Arab Emirates, College of Information Technology, UAE University, United Arab Emirates
dc.contributor.authorAddress Chehab, A.; American University of Beirut, Beirut, Lebanon; email: chehab@aub.edu.lb
dc.contributor.authorCorporate University: American University of Beirut; Faculty: Faculty of Engineering and Architecture; Department: Electrical and Computer Engineering;
dc.contributor.authorDepartment Electrical and Computer Engineering
dc.contributor.authorDivision
dc.contributor.authorEmail chehab@aub.cdu.lb; makki@uaeL1.ac.ae
dc.contributor.authorFaculty Faculty of Engineering and Architecture
dc.contributor.authorInitials Chehab, A
dc.contributor.authorInitials Patel, S
dc.contributor.authorInitials Makki, R
dc.contributor.authorOrcidID
dc.contributor.authorReprintAddress Chehab, A (reprint author), Amer Univ Beirut, Beirut, Lebanon.
dc.contributor.authorResearcherID
dc.contributor.authorUniversity American University of Beirut
dc.description.cited ABRAHAM J, 2002, INT WORKSH EL DES TE, P360; BINKLEY D, Patent No. 10237670; CHEHAB A, 2004, P IEEE INT WORKSH DE, P11; CHEHAB A, 2002, 6 WORLD MULT SYST CY; CHENG KT, 1993, IEEE T COMP AID DES; Germida A., 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034), DOI 10.1109-TEST.1999.805615; Ishida M., 2001, IEEE INT WORKSH DEF; Jiang W., 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034), DOI 10.1109-TEST.1999.805614; JIANG WL, 1999, IEEE DES AUT C, P976; Kruseman B., 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034), DOI 10.1109-TEST.1999.805613; LEVENDEL Y, 1986, INT FAULT TOL COMP S, P278; LI WN, 1989, IEEE T COMP AID DES; LIU J, 1996, IEEE P EC DES TEST M; MAJHI AK, 1996, 9 INT C VLSI DES, P418; MAKKI R, 1995, ITC, P892; MALAIYA YK, 1984, DESIGN TEST COMPUTER; Min YH, 1998, J ELECTRON TEST, V13, P51, DOI 10.1023-A:1008337200506; Mukherjee A, 2002, DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, 2002 PROCEEDINGS, P176; Needham W, 1998, INT TEST CONF P, P25; PLUSQUELLIC J, 1998, DFT, P93; PLUSQUELLIC JF, 1997, IEEE P INT TEST C, P40; Plusquellic JF, 1996, INTERNATIONAL TEST CONFERENCE 1996, PROCEEDINGS, P481; Sachdev M, 1998, INT TEST CONF P, P204; SCHULZ MH, 1987, 24 DES AUT C, P237, DOI 10.1145-37888.37923; Segura J, 1999, ELECTRON LETT, V35, P441, DOI 10.1049-el:19990359; SU S, 1995, J ELECTRON TEST, P23; Vinnakota B, 1998, INT TEST CONF P, P1027; Vinnakota B, 1996, 14TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, P483; WAICUKAUSKI JA, 1987, IEEE DESIGN TEST COM
dc.description.citedCount 1
dc.description.citedTotWOSCount 1
dc.description.citedWOSCount 1
dc.format.extentCount 12
dc.identifier.articleNo
dc.identifier.coden JTTAE
dc.identifier.pubmedID
dc.identifier.scopusID 33646580009
dc.identifier.url
dc.publisher.address VAN GODEWIJCKSTRAAT 30, 3311 GZ DORDRECHT, NETHERLANDS
dc.relation.ispartofConference
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dc.relation.ispartofConferenceDate
dc.relation.ispartofConferenceHosting
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dc.relation.ispartofConferenceSponsor
dc.relation.ispartofConferenceTitle
dc.relation.ispartofFundingAgency
dc.relation.ispartOfISOAbbr J. Electron. Test.-Theory Appl.
dc.relation.ispartOfIssue 1
dc.relation.ispartOfPart
dc.relation.ispartofPubTitle Journal of Electronic Testing: Theory and Applications (JETTA)
dc.relation.ispartofPubTitleAbbr J Electron Test Theory Appl JETTA
dc.relation.ispartOfSpecialIssue
dc.relation.ispartOfSuppl
dc.relation.ispartOfVolume 22
dc.source.ID WOS:000237023700002
dc.type.publication Journal
dc.subject.otherAuthKeyword Design for current testability
dc.subject.otherAuthKeyword Dynamic power supply current
dc.subject.otherAuthKeyword Fault simulation
dc.subject.otherAuthKeyword Resistive bridges
dc.subject.otherAuthKeyword Resistive opens
dc.subject.otherAuthKeyword VDSM
dc.subject.otherAuthKeyword Very deep sub-micron technologies
dc.subject.otherChemCAS
dc.subject.otherIndex Design for current testability
dc.subject.otherIndex Dynamic power supply current
dc.subject.otherIndex Fault simulation
dc.subject.otherIndex Resistive bridges
dc.subject.otherIndex Resistive opens
dc.subject.otherIndex VDSM
dc.subject.otherIndex Very deep sub-micron technologies
dc.subject.otherIndex Computer simulation
dc.subject.otherIndex Electric network analysis
dc.subject.otherIndex Electric power supplies to apparatus
dc.subject.otherIndex Performance
dc.subject.otherIndex Logic circuits
dc.subject.otherKeywordPlus
dc.subject.otherWOS Engineering, Electrical and Electronic


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