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Scaling of i DDT test methods for random logic circuits

Show simple item record Chehab A. Patel S. Makki R.
dc.contributor.editor 2006 2017-10-04T11:07:33Z 2017-10-04T11:07:33Z 2006
dc.identifier 10.1007/s10836-006-4835-z
dc.identifier.issn 09238174
dc.description.abstract We present a scaling methodology to improve i DDT fault coverage in random logic circuits. The study targets two i DDT test methods: Double Threshold i DDT and Delayed i DDT. The effectiveness of the scaling methodology is assessed through physical test measurements, and studied relative to process variation and impact on circuit performance. The scaling is made possible using a clustering methodology that can significantly improve fault coverage. The results show that without clustering, the effectiveness of the i DDT testing methods considered is greatly reduced as the circuit size increases. © 2006 Springer Science + Business Media, Inc.
dc.format.extent Pages: (11-22)
dc.language English
dc.publisher DORDRECHT
dc.relation.ispartof Publication Name: Journal of Electronic Testing: Theory and Applications (JETTA); Publication Year: 2006; Volume: 22; no. 1; Pages: (11-22);
dc.source Scopus
dc.title Scaling of i DDT test methods for random logic circuits
dc.type Article
dc.contributor.affiliation Chehab, A., American University of Beirut, Beirut, Lebanon, ECE Department, AUB, Lebanon
dc.contributor.affiliation Patel, S., University of North Carolina at Charlotte, Charlotte, NC 28223, United States
dc.contributor.affiliation Makki, R., College of Information Technology, UAE University, AL-Ain, United Arab Emirates, College of Information Technology, UAE University, United Arab Emirates
dc.contributor.authorAddress Chehab, A.; American University of Beirut, Beirut, Lebanon; email:
dc.contributor.authorCorporate University: American University of Beirut; Faculty: Faculty of Engineering and Architecture; Department: Electrical and Computer Engineering;
dc.contributor.authorDepartment Electrical and Computer Engineering
dc.contributor.faculty Faculty of Engineering and Architecture
dc.contributor.authorInitials Chehab, A
dc.contributor.authorInitials Patel, S
dc.contributor.authorInitials Makki, R
dc.contributor.authorReprintAddress Chehab, A (reprint author), Amer Univ Beirut, Beirut, Lebanon.
dc.contributor.authorUniversity American University of Beirut
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dc.description.citedCount 1
dc.description.citedTotWOSCount 1
dc.description.citedWOSCount 1
dc.format.extentCount 12
dc.identifier.coden JTTAE
dc.identifier.scopusID 33646580009
dc.relation.ispartOfISOAbbr J. Electron. Test.-Theory Appl.
dc.relation.ispartOfIssue 1
dc.relation.ispartofPubTitle Journal of Electronic Testing: Theory and Applications (JETTA)
dc.relation.ispartofPubTitleAbbr J Electron Test Theory Appl JETTA
dc.relation.ispartOfVolume 22
dc.source.ID WOS:000237023700002
dc.type.publication Journal
dc.subject.otherAuthKeyword Design for current testability
dc.subject.otherAuthKeyword Dynamic power supply current
dc.subject.otherAuthKeyword Fault simulation
dc.subject.otherAuthKeyword Resistive bridges
dc.subject.otherAuthKeyword Resistive opens
dc.subject.otherAuthKeyword VDSM
dc.subject.otherAuthKeyword Very deep sub-micron technologies
dc.subject.otherIndex Design for current testability
dc.subject.otherIndex Dynamic power supply current
dc.subject.otherIndex Fault simulation
dc.subject.otherIndex Resistive bridges
dc.subject.otherIndex Resistive opens
dc.subject.otherIndex VDSM
dc.subject.otherIndex Very deep sub-micron technologies
dc.subject.otherIndex Computer simulation
dc.subject.otherIndex Electric network analysis
dc.subject.otherIndex Electric power supplies to apparatus
dc.subject.otherIndex Performance
dc.subject.otherIndex Logic circuits
dc.subject.otherWOS Engineering, Electrical and Electronic

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