A study of continual flow pipelines on simultaneous multithreading processors

Abstract

With the dramatic increase in the number of mobile devices such as smartphones, tablets, etc... present in the market the need to develop systems-on-chip (SOC) increased correspondingly, which required architects to decrease the area occupied by cores, memories... while increasing the performance with every new generation of processors. Thus, the concept of simultaneous multithreading architectures (SMT) was introduced to ensure that performance continues to improve by taking advantage of the instruction level parallelism (ILP) found within an application code and-or between different applications running simultaneously. However, the conventional SMT architectures have a significant problem caused by cache contention between threads. This forces architects to increase cache size in order to reduce miss rates or develop deeper pipelines to allow a large number of instructions to start while waiting for the cache miss to be resolved. Both solutions, however, increase the core area and complexity. A recently proposed architecture named Continual Flow Pipelines (CFP) was introduced to address long latency cache misses in single-threaded applications without increasing chip area. In CFP, the pipeline is designed to be non-blocking, to allow independent instructions to continue execution while keeping the processor simple and without increasing cache size. However, when the instructions become ready, the CFP has to re-dispatch them into the pipeline wasting a number of valuable instructions cycles to perform that. In this thesis, we present a study of the advantages of each of these techniques in addressing the problem of long-latency instructions and explore whether integrating the two together will present any performance and throughput improvement. We also study if CFP implemented over Multicore architectures will provide better improvement than SMT. Our study shows that single-threaded CFP shows about 2.9percent improvement in throughput and SMT shows about 31percent improvement in cycles-instruction (CPI) over superscalar ar