NVSRAM Design with Enhanced Reset Capability for IoT Processors and In-Memory Compute Applications

Abstract

With the advent of technology, RRAM-based non-volatile SRAM cells are becoming a promising element for state-of-the-art IoT processor design. They allow fast parallel store/restore mechanisms, low store/restore energy consumption, compact cell area, and zero-standby power operation for purposes of traditional non-volatile processor memory storage designs. These designs, however, may suffer from a weak reset mechanism - where the low resistance state is programmed into a high resistance state. More recently, SRAM-based XNOR cell designs are used as the core bit-cell for in-memory compute array structure targeting binary neural network in-memory compute applications. In fact, Binarized Neural Networks manifest themselves as an efficient alternative to Deep Neural Networks on resource-limited devices with great potential for in-memory compute applications. In this thesis, we propose a novel non-volatile XNOR cell designs with enhanced Reset capability for purposes of nonvolatile processor applications. The proposed designs enhance the embedded SRAM cell pull-up capability during reset without compromising the functional cell aspect ratio while exploiting the XNOR cell cross-coupled pass-gate transistors. We study the proposed designs for high endurance window ranges and demonstrate up to 30% and 38% reduction in the energy and energy-delay product respectively compared to an equally sized traditional non-volatile XNOR cell. Process variations and program instability can further impact the reliability of non-volatile memory designs. The enhanced reset capability alleviates the impact of process variations resulting in enhanced restore yield. To evaluate this, we implement an error-injection algorithm on a BNN network model built using Larq. We demonstrate <1% impact on test accuracy for the proposed design due to the enhanced reset capability compared to 8% accuracy loss for the traditional design.