NOVEL MEMRISTOR-BASED HYBRID ADDER DESIGN WITH ML APPLICATIONS

Abstract

The use of memristors in logic circuits opens new pathways for the exploring of novel efficient full adder circuits. n our thesis, we first study the memristor dynamics, and then we explore the different approaches, found in the literature, for memristor-based logic computations. We then propose two Memristor Ratioed Logic (MRL) based novel XOR/XNOR gates as the core components of the adder circuit. We employ the gates in the design of four versions of a hybrid one-bit full adder cells. We evaluate the energy delay and area tradeoffs of the proposed cells standalone and in the context of 32-bit adders. The smallest full adder uses 10 transistors and 4 memristors. The ‘best’ full adder cell uses 14 transistors and 4 memristors. The corresponding 32-bit adder demonstrates 1.6ns worst-case delay, and an average of 8.5ns.pJ energy-delay product. More importantly, it does not require the insertion of buffers between stages and hence the area of the 32-bit adder drops significantly. Finally, we study the implications of memristor process variations in terms of memristor variability and memristor stuck-at faults on the adder design in two applications: (1) image convolution, and (2) convolutional neural networks for classifying handwritten digits in the MNIST database. For the former, the memristor variability had a minimal effect on the quality of output images, but the stuck- at faults effects resulted in low-quality images. For the latter, the classification accuracy decreases dramatically when memristance variability exceeds 20%. We relied on HSpice for our simulations, and we used the VTEAM model memristor, and the 65nm CMOS predictive technology models.