A Strength Pareto Evolutionary Algorithm for Optimizing System-On-Chip Test Schedules
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World Scientific Publishing Co.
Abstract
System-on-chip (SOC) has become a mainstream design practice that integrates intellectual property cores on a single chip. The SOC test scheduling problem maximizes the simultaneous test of all cores by determining the order in which various cores are tested. The problem is tightly coupled with the test access mechanism (TAM) bandwidth and wrapper design. This paper presents a strength Pareto evolutionary algorithm for the SOC test scheduling problem with the objective of minimizing the power-constrained test application time, wrapper design and TAM assignment in flat and hierarchical core-based systems. We demonstrate the effectiveness of the method using the ITC'02 benchmarks. © 2018 World Scientific Publishing Europe Ltd.
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Keywords
Spea2, System-on-chip, Test scheduling, Application specific integrated circuits, Evolutionary algorithms, Hierarchical systems, Integrated circuit testing, Programmable logic controllers, Scheduling, Soc test scheduling, Strength pareto evolutionary algorithm, System on chips (soc), System-on-chip test, Test access mechanism, Test application time, Integrated circuit design