A Strength Pareto Evolutionary Algorithm for Optimizing System-On-Chip Test Schedules

Simple item page
dc.contributor.authorMarrouche, Wissam
dc.contributor.authorFarah, Rana
dc.contributor.authorHarmanani, Haidar M.
dc.contributor.departmentDepartment of Electrical and Computer Engineering
dc.contributor.facultyMaroun Semaan Faculty of Engineering and Architecture (MSFEA)
dc.contributor.institutionAmerican University of Beirut
dc.date.accessioned2025-01-24T11:29:38Z
dc.date.available2025-01-24T11:29:38Z
dc.date.issued2018
dc.description.abstractSystem-on-chip (SOC) has become a mainstream design practice that integrates intellectual property cores on a single chip. The SOC test scheduling problem maximizes the simultaneous test of all cores by determining the order in which various cores are tested. The problem is tightly coupled with the test access mechanism (TAM) bandwidth and wrapper design. This paper presents a strength Pareto evolutionary algorithm for the SOC test scheduling problem with the objective of minimizing the power-constrained test application time, wrapper design and TAM assignment in flat and hierarchical core-based systems. We demonstrate the effectiveness of the method using the ITC'02 benchmarks. © 2018 World Scientific Publishing Europe Ltd.
dc.identifier.doihttps://doi.org/10.1142/S1469026818500104
dc.identifier.eid2-s2.0-85048655892
dc.identifier.urihttp://hdl.handle.net/10938/27276
dc.language.isoen
dc.publisherWorld Scientific Publishing Co.
dc.relation.ispartofInternational Journal of Computational Intelligence and Applications
dc.sourceScopus
dc.subjectSpea2
dc.subjectSystem-on-chip
dc.subjectTest scheduling
dc.subjectApplication specific integrated circuits
dc.subjectEvolutionary algorithms
dc.subjectHierarchical systems
dc.subjectIntegrated circuit testing
dc.subjectProgrammable logic controllers
dc.subjectScheduling
dc.subjectSoc test scheduling
dc.subjectStrength pareto evolutionary algorithm
dc.subjectSystem on chips (soc)
dc.subjectSystem-on-chip test
dc.subjectTest access mechanism
dc.subjectTest application time
dc.subjectIntegrated circuit design
dc.titleA Strength Pareto Evolutionary Algorithm for Optimizing System-On-Chip Test Schedules
dc.typeArticle

Files

Original bundle

Now showing 1 - 1 of 1
Thumbnail Image
Name:
2018-8149.pdf
Size:
1002.37 KB
Format:
Adobe Portable Document Format
Download

Collections

Department of Electrical and Computer Engineering