A dynamically reconfigurable register file for soft processor cores architecture and characteristics - by Haytham Hussein Hamadeh

dc.contributor.author	Hamadeh, Haytham Hussein
dc.contributor.department	Department of Electrical and Computer Engineering
dc.contributor.faculty	Faculty of Engineering and Architecture
dc.contributor.institution	American University of Beirut
dc.date	2008
dc.date.accessioned	2012-06-13T07:11:19Z
dc.date.available	2012-06-13T07:11:19Z
dc.date.issued	2008
dc.description	Thesis (M.E.)--American University of Beirut, Dept. of Electrical and Computer Engineering, 2008.;"Advisor : Dr. Mazen Saghir, Assistant Professor , Department of Electrical and Computer Engineering--Member of Committee : Dr. Ayman Kayssi, Professor , Dep
dc.description	Bibliography : leaves 89-91.
dc.description.abstract	This thesis describes the architecture of a dynamically reconfigurable, multi-po rted register file for soft processor cores. The register file is designed using block RAMs found in high-density FPGAs like the Xilinx Virtex-4. The latency of the register
dc.format.extent	xvi, 89 leaves : ill. 30 cm.
dc.identifier.uri	http://hdl.handle.net/10938/7665
dc.language.iso	en
dc.relation.ispartof	Theses, Dissertations, and Projects
dc.subject.classification	ET:005131 AUBNO
dc.subject.lcsh	Adaptive computing systems
dc.subject.lcsh	Microprocessors
dc.title	A dynamically reconfigurable register file for soft processor cores architecture and characteristics - by Haytham Hussein Hamadeh
dc.type	Thesis

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