Specification construction using equivalence relations and SMT solvers -

Abstract

We propose an approach to write formal specifications. Our approach partitions the (possibly infinite) state-space of the specification into a finite number of equivalence classes. The partition is defined by the equivalence relation induced by the valuations of a finite set of first-order logic formulae. Our work builds on existing work, which presents a method for writing specifications, along with a preliminary text-based implementation. In this thesis, we extend the current implementation with a graphical-user interface, and use this implementation to conduct experiments with the goal of demonstrating the value of the method by using it to write difficult and intricate specifications, and also using the experimental results as feedback for further improvements to the method.