RTL level verification

Abstract

Design-for-Test, Logic Built-in Self Test, memory technology mapping and clocking concerns require team-months of verification time as they traditionally happen at gate level where concerns are highly coupled and verification requires several design flow iterations. We present a novel concern oriented methodology that enables automatic insertion of memory related concerns at the Register Transfer Level (RTL). It separates concerns and thereby reduces their coupling. It also lifts verification to the RTL level and reduces the design iterations. The methodology involves three main phases: (1) flipflop inference and instantiation algorithms that handle parametric RTL modules, (2) transformations that take entry RTL and produce RTL modules where memory elements are separated from functionality, and (3) a concern weaving tool that automatically inserts memory related design concerns implemented in recipe files into the RTL modules. We prove the transformations sound. We also use formal methods to validate the implementation of the transformations. The methodology speeds up verification by lifting memory related concern weaving to RTL. It also allows for smaller and faster verification environments due to automatic separation and insertion of concerns. This enables partial concern verification with low overhead which in turn reduces the verification design size and makes emulation possible. In addition, the methodology increases the productivity of designers by (1) allowing debugging to occur at a higher level of abstraction, and (2) logic and concern designers to work independently due to decoupling of concerns. The automatic memory element inference of the methodology alleviates the designers from understanding the concern implementations, and lets them focus on the functionality instead. We implemented the methodology in a tool that is currently used in an industrial setting. The methodology reduced design verification time by more than 40percent. It is applicable on non-parametric designs as well as parametric design