Super fast physics-based methodology for accurate memory yield prediction

dc.contributor.authorJoshi, Rajiv V.
dc.contributor.authorKim, Keunwoo
dc.contributor.authorKanj, Rouwaida N.
dc.contributor.authorBhoj, Ajay N.
dc.contributor.authorZiegler, Matthew M.
dc.contributor.authorOldiges, Phil J.
dc.contributor.authorKerber, Pranita
dc.contributor.authorWong, Robert C.
dc.contributor.authorHook, Terence B.
dc.contributor.authorSaroop, Sudesh
dc.contributor.authorRadens, Carl J.
dc.contributor.authorYeh, Chunchen
dc.contributor.departmentDepartment of Electrical and Computer Engineering
dc.contributor.facultyMaroun Semaan Faculty of Engineering and Architecture (MSFEA)
dc.contributor.institutionAmerican University of Beirut
dc.date.accessioned2025-01-24T11:29:15Z
dc.date.available2025-01-24T11:29:15Z
dc.date.issued2015
dc.description.abstractWe propose an efficient physics-based mixed-mode statistical simulation methodology for nanoscale devices and circuits. Here, 3-D Technology Computer Aided Design models pose a barrier for efficient simulation of variability as they generally involve millions of nodes in their mesh representations. The proposed methodology, which has been implemented for FinFET/tri-gate static random access memory (SRAM) design, overcomes this barrier by leveraging advanced physics-based 2-D (P2-D) devices with optimized meshes that are derived from 3-D FinFET models with tuned device parasitics. This enables physics-based simulation as well as physics-based variability input parameters. To improve accuracy, an embedded automated flow enables extraction of all external nodal parasitics, directly from a 3-D FinFET circuit layout representation. The circuits consisting of advanced P2-D devices are then back annotated with the nodal parasitics to enable fast and accurate SRAM dynamic margin mixed-mode simulations. Results demonstrate up to 200x speedup compared with traditional 3-D device simulations, and around five orders of magnitude wall clock time improvement on account of fast statistical methodologies, which are superior in comparison with traditional Monte Carlo analysis. This makes it feasible to supplant often inaccurate compact model-based simulations by true mixed-mode device simulations in statistical engines. The proposed physics-based methodology is also shown to corroborate well with hardware measurements. © 1993-2012 IEEE.
dc.identifier.doihttps://doi.org/10.1109/TVLSI.2014.2313815
dc.identifier.eid2-s2.0-85027929450
dc.identifier.urihttp://hdl.handle.net/10938/27148
dc.language.isoen
dc.publisherInstitute of Electrical and Electronics Engineers Inc.
dc.relation.ispartofIEEE Transactions on Very Large Scale Integration (VLSI) Systems
dc.sourceScopus
dc.subjectCapacitance
dc.subjectFast statistical sampling
dc.subjectFinfet
dc.subjectPhysics-based models
dc.subjectStatic noise margin (snm)
dc.subjectStatic random access memory (sram)
dc.subjectTechnology computer aided design (tcad)
dc.subjectComputer aided design
dc.subjectDesign
dc.subjectIntegrated circuits
dc.subjectMonte carlo methods
dc.subjectRandom access storage
dc.subjectSampling
dc.subjectStatic noise margin
dc.subjectStatic random access memory
dc.subjectStatistical sampling
dc.subjectTechnology computer aided design
dc.subjectStatic random access storage
dc.titleSuper fast physics-based methodology for accurate memory yield prediction
dc.typeArticle

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