A dynamically reconfigurable cache architecture for soft core processors - by Marilise Maroun Makhoul
Abstract
A dynamically reconfigurable Level-1 data cache that can adapt its architecture according to the application is designed and implemented. A selection of 64 out of thousands of possible configurations is analyzed by means of simulation. The analysis of the
Description
Thesis (M.E.)--American University of Beirut, Dept. of Electrical and Computer Engineering, 2009.;"Advisor : Dr. Mazen Saghir, Associate Professor ,Department of Electrical and Computer Engineering--Member of Committee: Dr. Ayman Kayssi, Professor ,Depart
Bibliography : leaves 65-67.
Bibliography : leaves 65-67.