RRAM Device Models: A Comparative Analysis with Experimental Validation

dc.contributor.authorHajri, Basma
dc.contributor.authorAziza, Hassen
dc.contributor.authorMansour, Mohammad M.
dc.contributor.authorChehab, Ali
dc.contributor.departmentDepartment of Electrical and Computer Engineering
dc.contributor.facultyMaroun Semaan Faculty of Engineering and Architecture (MSFEA)
dc.contributor.institutionAmerican University of Beirut
dc.date.accessioned2025-01-24T11:29:49Z
dc.date.available2025-01-24T11:29:49Z
dc.date.issued2019
dc.description.abstractResistive Random Access Memories (RRAM) have recently shown outstanding characteristics such as high-scalability, high-speed, high-density, and low-energy operation. A simple and accurate model is crucial for rapid design and verification when using RRAM devices at the circuit level. The appropriate model selection gives insight into the behavior of RRAM as well as the efficient use of its unique properties. This work intends to guide the circuit designers in selecting the most appropriate RRAM model for their applications. We introduce a complete set of evaluation criteria for memristor models: Type of model, type of switching, genericity, complexity, compatibility with actual physical switching mechanisms, linearity, symmetry, voltage/current control, hard set/soft reset, support electroforming, support for high programming signal frequencies, existence of a threshold, voltage level, timing dependence, temperature dependence and variability. This study compares the main existing RRAM models and summarizes the results in a table showing the main features and limitations of each model. Through extensive simulations and comparisons with experimental data, we provide an analysis and a validation of the reviewed models within the same simulation environment, ranging from individual elementary cells to large memory arrays. Furthermore, we provide a single and unique Verilog-A code integrating all the compared models. © 2019 IEEE.
dc.identifier.doihttps://doi.org/10.1109/ACCESS.2019.2954753
dc.identifier.eid2-s2.0-85077787972
dc.identifier.urihttp://hdl.handle.net/10938/27315
dc.language.isoen
dc.publisherInstitute of Electrical and Electronics Engineers Inc.
dc.relation.ispartofIEEE Access
dc.sourceScopus
dc.subjectExperimental validation
dc.subjectMemristor models
dc.subjectModel comparison
dc.subjectModels assessment
dc.subjectResistive random access memory (rram)
dc.subjectSimulation
dc.subjectVerilog-a
dc.subjectMemristors
dc.subjectTemperature distribution
dc.subjectExperimental validations
dc.subjectMemristor
dc.subjectRram
dc.titleRRAM Device Models: A Comparative Analysis with Experimental Validation
dc.typeArticle

Files

Original bundle

Now showing 1 - 1 of 1
Loading...
Thumbnail Image
Name:
2019-7760.pdf
Size:
3.03 MB
Format:
Adobe Portable Document Format