RRAM Device Models: A Comparative Analysis with Experimental Validation
| dc.contributor.author | Hajri, Basma | |
| dc.contributor.author | Aziza, Hassen | |
| dc.contributor.author | Mansour, Mohammad M. | |
| dc.contributor.author | Chehab, Ali | |
| dc.contributor.department | Department of Electrical and Computer Engineering | |
| dc.contributor.faculty | Maroun Semaan Faculty of Engineering and Architecture (MSFEA) | |
| dc.contributor.institution | American University of Beirut | |
| dc.date.accessioned | 2025-01-24T11:29:49Z | |
| dc.date.available | 2025-01-24T11:29:49Z | |
| dc.date.issued | 2019 | |
| dc.description.abstract | Resistive Random Access Memories (RRAM) have recently shown outstanding characteristics such as high-scalability, high-speed, high-density, and low-energy operation. A simple and accurate model is crucial for rapid design and verification when using RRAM devices at the circuit level. The appropriate model selection gives insight into the behavior of RRAM as well as the efficient use of its unique properties. This work intends to guide the circuit designers in selecting the most appropriate RRAM model for their applications. We introduce a complete set of evaluation criteria for memristor models: Type of model, type of switching, genericity, complexity, compatibility with actual physical switching mechanisms, linearity, symmetry, voltage/current control, hard set/soft reset, support electroforming, support for high programming signal frequencies, existence of a threshold, voltage level, timing dependence, temperature dependence and variability. This study compares the main existing RRAM models and summarizes the results in a table showing the main features and limitations of each model. Through extensive simulations and comparisons with experimental data, we provide an analysis and a validation of the reviewed models within the same simulation environment, ranging from individual elementary cells to large memory arrays. Furthermore, we provide a single and unique Verilog-A code integrating all the compared models. © 2019 IEEE. | |
| dc.identifier.doi | https://doi.org/10.1109/ACCESS.2019.2954753 | |
| dc.identifier.eid | 2-s2.0-85077787972 | |
| dc.identifier.uri | http://hdl.handle.net/10938/27315 | |
| dc.language.iso | en | |
| dc.publisher | Institute of Electrical and Electronics Engineers Inc. | |
| dc.relation.ispartof | IEEE Access | |
| dc.source | Scopus | |
| dc.subject | Experimental validation | |
| dc.subject | Memristor models | |
| dc.subject | Model comparison | |
| dc.subject | Models assessment | |
| dc.subject | Resistive random access memory (rram) | |
| dc.subject | Simulation | |
| dc.subject | Verilog-a | |
| dc.subject | Memristors | |
| dc.subject | Temperature distribution | |
| dc.subject | Experimental validations | |
| dc.subject | Memristor | |
| dc.subject | Rram | |
| dc.title | RRAM Device Models: A Comparative Analysis with Experimental Validation | |
| dc.type | Article |
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