Fast Column Message-Passing Decoding of Low-Density Parity-Check Codes

Abstract

A new fast column message-passing (FCMP) schedule for decoding LDPC codes is presented and investigated in this brief. FCMP converges in half the number of iterations compared to existing serial decoding schedules, has a significantly lower computational complexity than residual-belief-propagation (RBP)-based schedules, and consumes less power compared to state-of-the-art schedules. An FCMP decoder architecture supporting IEEE 802.11ad (WiGig) LDPC codes is presented. The architecture is synthesized using the TSMC 40 nm CMOS technology node and operates at a clock frequency of 200 MHz. The decoder achieves a throughput of 8.4 Gbps while consuming 72 mW of power. This results in an energy efficiency of 8.6 pJ/bit, which is the best-reported energy-efficiency in the literature for a WiGig LDPC decoder. © 2004-2012 IEEE.