Novel 4 GHz interleaved SRAM cells with asymmetrical precharge in 45 nm PDSOI technology

Abstract

Novel 9T/8T SRAM cell designs are demonstrated using a fully functional 75-kb L1-cache compatible interleaved hardware based design in 45 nm SOI. An integrated read stack, together with an asymmetrical precharge topology, leads to significant improvement in performance and stability. The proposed cells' yield outperforms that of register file like cells as well as other literature cells. The usage of a larger number of cells on bitlines through statistical simulations indicates that the new cells improve the array efficiency for domino based designs. The extension of the work to 32 nm technology shows the scalability of these cells with lower operating voltage, compared with conventional 6T/8T cells. Hardware based key features include improved read performance/stability, half select stability, and the ability to operate with single read and write wordline over register file like 8T cell. The measured access time improvement is shown to be more than 15% and a Vcsmin reduction of 170 mV is demonstrated at © 2014 IEEE.