Hardware architectures for accelerating image registration applications -

Abstract

Image registration (IR) is a universal task which occurs in countless image analysis applications, including remote sensing, medicine, cartography and computer vision. This process is computationally intensive due to stringent real-time constraints and huge amounts of data used. The need for a general registration method that is both fast and accurate has motivated researchers to focus on developing fast and reliable registration platforms. Existing IR platforms include FPGA, GPU, CPU and heterogeneous-based architectures. Studies show that hardware-oriented platforms behave much better than software based platforms. However, they are very difficult to modify. In this thesis, we propose a new IR hardware-based architecture. This architecture dynamically controls different algorithms using the PVV (Percentage of Valid Voxels). It makes use of a hybrid optimization technique (gradient descent and simplex). Finally, it adapts several parallel aspects to improve the overall performance (sub-volume, pixel and operational level parallelism). The choices of the IR algorithms were based on MATLAB simulations. In these simulations, the mostly used algorithms are implemented and then tested for speed and accuracy. Finally, the new design is implemented and tested using Xilinx. Experiments show that the proposed architecture outperforms numerous other existing designs. Its average execution time is 3.1 minutes.