Low power stochastic SIMD hardware for error tolerant applications -

Abstract

Many emerging applications are error tolerant by nature: their operations are considered “correct” even if the underlying hardware is erroneous to a certain extent. Under these circumstances, fault-correction mechanisms turn out to be unnecessary. This gave birth to “stochastic processors” that are under-designed and allow results not to be fully correct. Relaxing the hardware correctness requirements as a way to reduce energy consumption is a major trend because of the emergence of green electronics on one hand and the boom in portable devices with limited battery capacity on the other. This thesis discusses error tolerant applications and their characteristics, and proposes a new low power hardware that takes advantage of those characteristics in the aim of saving power. Since these applications are data intensive, parallelizing them yields even more pronounced power saving results, and thus the choice of a SIMD hardware. The energy saving is achieved by applying Voltage Scaling on the parts of the hardware that run the parallelized data parts of the application, while keeping the control parts secured via normal voltage operation. Our design saved up to 35percent per instruction for 16-bit SIMD and 65percent per instruction for 8-bit SIMD as compared to an exact SISD processor, and 83percent when applying voltage scaling to SIMD.