dc.contributor.author |
Stockman, Melissa, |
dc.date |
2014 |
dc.date.accessioned |
2015-02-03T10:23:55Z |
dc.date.available |
2015-02-03T10:23:55Z |
dc.date.issued |
2014 |
dc.date.submitted |
2014 |
dc.identifier.other |
b17931599 |
dc.identifier.uri |
http://hdl.handle.net/10938/10039 |
dc.description |
Dissertation (Ph.D.)-- American University of Beirut, Department of Electrical and Computer Engineering, 2014. |
dc.description |
Chairman of Committee : Dr. Karim Kabalan, Professor, Electrical and Computer Engineering ; Advisor : Dr. Haitham Akkary, Associate Professor, Electrical and Computer Engineering ; Co-Advisor : Dr. Mariette Awad, Assistant Professor, Electrical and Computer Engineering ; Committee Members: Dr. Mazen Saghir, Associate Professor, Texas AandM University at Qatar ; Dr. Roman Neruda, Researcher, Institute of Computer Science, Academy of Sciences of the Czech Republic. |
dc.description |
Includes bibliographical references (leaves 80-88) |
dc.description.abstract |
Processor resource needs vary across applications as well as within individual applications. Some programs may be memory intensive; others may have a high amount of branching, while others may need many floating point computations. Maximal configurations waste power when an application’s performance would not be degraded running on a lower power configuration. By adjusting a processor’s configuration during application runtime, it is possible to save power without a performance cost. But maximizing performance and minimizing power are two conflicting objectives. Knowing what configuration will be the best at a given time for a running program is not easily determined. The majority of previous works have attempted to adjust a small number of microarchitectural parameters at a time. This detracts from the overall performance-power achievements that can be attained by adjusting a large number of parameters together. Additionally, none of these previous works have taken into consideration the fact that processor variability affects the model’s effectiveness. Our framework allows for building separate loadable models for chips with different leakage percentages. In this dissertation we propose using a machine learning technique to determine maximal performance configurations during program execution. Specifically we use ‘support vector regression’ (SVR) to determine the best configurations for a given power level which maximizes performance in terms of IPC while constraining power to some user defined level. This research aims to reduce power in a global manner by determining maximal performance configurations for more than 17 variable microarchitectural parameters simultaneously in order to benefit from any interaction these units may have on each other. This number of variables makes it impossible to try every combination of all parameters in a trial and error method; therefore a machine learning approach was taken. We provide a framework |
dc.format.extent |
xiii, 88 leaves : illustrations ; 30 cm |
dc.language.iso |
eng |
dc.relation.ispartof |
Theses, Dissertations, and Projects |
dc.subject.classification |
ED:000043 AUBNO |
dc.subject.lcsh |
Support vector machines. |
dc.subject.lcsh |
Computer architecture. |
dc.subject.lcsh |
Microprocessors. |
dc.subject.lcsh |
Adaptive computing systems. |
dc.subject.lcsh |
Machine learning. |
dc.subject.lcsh |
Artificial intelligence. |
dc.title |
A unified approach to maximizing run-time performance on power constrained adaptive processors using support vector regression - |
dc.type |
Dissertation |
dc.contributor.department |
American University of Beirut. Faculty of Engineering and Architecture. Department of Electrical and Computer Engineering. degree granting institution. |