Architecture performance simulator for the disjoint out-of-order execution processor (DOE) and the OpenDOE API -

Abstract

Traditional methods of increasing single-core CPU performance have been very effective until designers hit the “Power Wall”. In order to overcome this issue, designers switched to multi-core architectures. This architectural switch to multicore CPUs has aided multitasking and multiprocessing on computers. However, the issue that remains is increasing the performance of a single process on a multicore chip. Many solutions were presented. Some were architectural techniques like speculative multithreading (SpMT) while others were higher-level software techniques like the OpenMP API. These techniques were successful on many applications, but those with an intrinsically sequential nature remained troublesome. This is due to the long delays and large power consumption that are incurred from the continuous inter-core communication, which has to occur between the threads, when the sequential nature of the application is explicit. In addition, APIs, like OpenMP, require advanced parallel programming skills that make the task complex for most programmers. Therefore, what we need is a multicore architecture that can divide a single application onto its different cores, while minimizing the penalties and overhead due to inter-core communication, as well as minimizing the effort required by the programmer. We are presenting the performance simulation of a processor that complies with the DOE architecture. The DOE, or Disjoint Out-of-Order Execution, processor is a latency tolerant, multicore system connected in a ring network. A single process is divided amongst the different cores using new instructions that we defined in accordance with the DOE architecture. We also introduced the OpenDOE API, a programming interface that allows the programmers to specify, using certain directives, the parallel regions and dependent variables. These pragmas are, then, translated by the compiler to our new instructions. The SimpleScalar tool set was used for the performance simulator and the PISA-MIPS instruction set was adopt