Rate-compatible coding : an inter-frame coding scheme and architecture-aware construction of Raptor codes -

Abstract

Coping with wireless channel variability is a major challenge in channel coding. Typically, feedback-based techniques such as link adaptation and hybrid automatic-repeat-request (HARQ) are used to match the appropriate code-rate to the instantaneous channel quality, in order to achieve high-throughput communication over varying wireless channel conditions. Rate-compatible coding is a crucial element of HARQ schemes, and therefore has been subject to intense research in recent years. In this dissertation, two related topics on rate-compatible coding are considered. First, the channel variation problem is considered in the broadcast communication scenario, in which schemes such as HARQ performs poorly. Drawing from the analogy between basic automatic-repeat-request and erasure coding, we propose to incorporate the rate-decreasing process into frame-level coding to achieve better complexity versus coding-performance tradeoff. The proposed scheme is called increment-based inter-frame coding. The corresponding coding algorithms and architectures are developed, and the coding performance of the scheme is assessed via asymptotic analysis and simulations. The results show that the proposed scheme yields higher data-rates compared to other conventional schemes such as HARQ and the state-of-the-art two-stage scheme involving both error-correcting and erasure coding. With regard to rate-compatible coding, the impact of the proposed scheme is two-fold: 1) it extends the application space of rate-compatible codes, and 2) imposes new design-requirements on these codes. Second, Raptor codes are proposed to be deployed as rate-compatible codes at the physical layer. The motivation is that Raptor features could ensure good performance of these codes under various communication scenarios, including the proposed inter-frame coding scheme. However, these features themselves make the design of hardware-efficient decoders more challenging. A code design flow is thus proposed to combine the aspects of coding-performance and hardware