Distributed FPGA-based acceleration of big data analytics in the data center environment.

Abstract

Several research studies have shown that Big data, as a largescale phenomenon, is creating substantial value for the world’s economy by boosting the productivity and competitiveness of private-sector businesses and public enterprises, and thus it is generating extensive economic surplus for consumers. However, the computational limitations of general-purpose processor-based data centers are preventing businesses from fully integrating Big data architectures in their business model. A widely accepted solution to this problem consists of supplementing microprocessors with application-specific hardware accelerators. Although a wide-ranging literature exists on the benefits of employing Field Programmable Gate Arrays (FPGAs) as hardware accelerators in the data center environment, FPGAs have not been extensively deployed there for two reasons: first, the lack of a scalable and power-efficient data center deployment model for FPGAs, and second, the complexity of programming and developing FPGA-based hardware accelerators for data center workloads. In this thesis, we address two problems: (1) the scalable deployment of FPGA platforms, and (2) the design and implementation of FPGA-based hardware accelerators for Deep Learning Big Data workloads. To address the first problem, a scalable and power-efficient Network-Attached-Accelerator (NAA) system architecture is proposed. The proposed NAA system architecture allows the seamless and efficient integration of FPGA-based platforms in existing data center architectures. Experimental Results showed that orders-of-magnitude improvements in performance can be achieved in certain applications. Then, to address the second problem, we propose a design methodology for mapping Deep Convolutional Neural Network (ConvNet) inference workloads to FPGA hardware accelerators. We employed our methodology to accelerate AlexNet, a popular computationally intensive ConvNet used for accurate image classification, and we showed that our design can achieve a potential performance of up to