Optimized ASIC Accelerator Chips for LDPC Decoders by Joint Algorithm, Architecture, and Circuit Co-Design

Abstract

Multi-Gb/s low-density-parity-check (LDPC) decoding is required for contemporary digital communication standards, like the 5G New Radio, IEEE 802.11 n/ac/ax (WiFi), and IEEE 802.11ad (WiGig), among others. Efficient application-specific integrated circuit (ASIC) implementation of the multi-Gb/s LDPC decoders requires fast-converging algorithms, high-throughput architectures, and optimized circuit choices. This work proposes and implements the algorithm, architecture, and circuit co-design approach for the development of optimized ASIC accelerator chips for LDPC decoders. Algorithmically, fast-converging schedules for decoding of LDPC codes, viz. interlaced column-row message-passing (ICRMP), and fast column-message passing (FCMP) schedules are proposed and investigated in this work. The proposed schedules converge double the speed of already existing fast-converging schedules, which are serial ones and converge two times the speed of initially proposed flooding schedule for LDPC decoding; the proposed schedules converge four times the speed of the flooding schedule with moderate increase in complexity, compared to the serial decoding schedules.

At the architectural level, multi-Gb/s architectures are proposed for the row message-passing (RMP) version of existing serial decoding schedules by targeting IEEE 802.11n/ac/ax (WiFi) LDPC decoder, and for the proposed FCMP schedule by targeting IEEE 802.11ad (WiGig) LDPC decoder. Circuit-level techniques are then proposed, and an optimized VLSI design of the targeted IEEE 802.11n/ac/ax LDPC decoder is synthesized using the TSMC 40nm CMOS process. The synthesis results of the implementation outperform state-of-the-art in terms of throughput/area. The proposed FCMP-based decoder architecture, for IEEE 802.11ad LDPC codes, is also synthesized using the same technology node, and the design achieves a throughput of 8.4 Gb/s while operating at a clock frequency of only 200 MHz, which enables the decoder to achieve the best-reported energy-efficiency of 8.6 pJ/bit, for IEEE 802.11ad LDPC decoders. Finally, an energy-efficient and high-throughput multi-core hardware architecture is presented and physically implemented as an ASIC chip. The implemented ASIC chip achieves a peak throughput of 15 Gb/s while operating at a clock frequency of 250MHz. The achieved throughput and the corresponding energy-efficiency are the best reported in the literature for an IEEE 802.11n/ac/ax LDPC decoder.