Robustness Guided Verification

Abstract

Exhaustive and thorough testing is the ideal form of testing for any system; it would not be possible for such a system to fail when all possible outcomes of its operation are known to succeed. However, with complex systems where the factors can be practically infinite, exhaustive testing is not feasible nor efficient. Novel approaches to testing systems and verifying that they adhere to their specifications are much needed. These approaches have to be able to test a wide variety of systems without necessarily knowing how these systems work. Such approaches to testing could potentially expose failures in systems with certain conditions that the tester could not have possibly imagined and consciously tested for. However, such approaches would be delegated to testing systems of high complexity, often with practically infinite parameter spaces. Therefore, testing algorithms have to be able to work with a limited set of possibilities, aiming to discover areas in which certain combinations of input parameters cause a failure in the system under test. Rare fail estimation is of particular importance in non-volatile memory cells such as the STT-MTJ based latch. Applying such novel approaches to non-volatile memory cells may accelerate yield estimation beyond what traditional tools are capable of. However, multiple tools are required to interoperate to integrate simulation of electric circuits with frameworks that implement such approaches. The tools required need to easily integrate Verilog-AMS models into ngspice, parametrize SPICE circuits from code, run several SPICE simulations in parallel. This allows to compute the ground truth in order to verify the accuracy of the Active Learning algorithm’s predictions, run SPICE simulations from within the Active Learning framework, be efficient with resource usage (such as memory), and execute in minimal time in order for the approach to be useful over more traditional approaches.