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A dynamically reconfigurable cache architecture for soft core processors - by Marilise Maroun Makhoul
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| dc.contributor.author | Makhoul, Marilise Maroun |
| dc.date.accessioned | 2012-06-13T07:31:51Z |
| dc.date.available | 2012-06-13T07:31:51Z |
| dc.date.issued | 2009 |
| dc.identifier.uri | http://hdl.handle.net/10938/8387 |
| dc.description | Thesis (M.E.)--American University of Beirut, Dept. of Electrical and Computer Engineering, 2009.;"Advisor : Dr. Mazen Saghir, Associate Professor ,Department of Electrical and Computer Engineering--Member of Committee: Dr. Ayman Kayssi, Professor ,Depart |
| dc.description | Bibliography : leaves 65-67. |
| dc.description.abstract | A dynamically reconfigurable Level-1 data cache that can adapt its architecture according to the application is designed and implemented. A selection of 64 out of thousands of possible configurations is analyzed by means of simulation. The analysis of the |
| dc.format.extent | xiii, 67 leaves : ill. (some col.) 30 cm. |
| dc.language.iso | eng |
| dc.relation.ispartof | Theses, Dissertations, and Projects |
| dc.subject.classification | ET:005244 AUBNO |
| dc.subject.lcsh | Adaptive computing systems |
| dc.subject.lcsh | Cache memory |
| dc.subject.lcsh | Microprocessors |
| dc.title | A dynamically reconfigurable cache architecture for soft core processors - by Marilise Maroun Makhoul |
| dc.type | Thesis |
| dc.contributor.department | American University of Beirut. Faculty of Engineering and Architecture. Department of Electrical and Computer Engineering |
