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A novel 16x64 2R-1W low power register-file with a stacked SRAM leakage suppression scheme - by Nadida Ghassan Raad.

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dc.contributor.author Raad, Nadida Ghassan.
dc.date.accessioned 2012-06-13T07:35:56Z
dc.date.available 2012-06-13T07:35:56Z
dc.date.issued 2012
dc.identifier.uri http://hdl.handle.net/10938/8810
dc.description Thesis (M.E.)--American University of Beirut, Department of Electrical and Computer Engineering, 2012.;"Advisor : Dr. Mohammad Mansour, Associate Professor, Department of Electrical and Computer Engineering--Members of Committee : Dr. Ayman Kayssi, Profes
dc.description Includes bibliographical references (leaves 96-99)
dc.description.abstract With technology scaling down below 90 nm, and the number of transistors on-chip significantly increasing, power management has become a critical issue in modern integrated circuits (IC). One of the most important power-critical components in current desig
dc.format.extent xvi, 99 leaves : ill. 30 cm.
dc.language.iso eng
dc.relation.ispartof Theses, Dissertations, and Projects
dc.subject.classification ET:005612 AUBNO
dc.subject.lcsh Cache memory.
dc.subject.lcsh Random access memory.
dc.subject.lcsh Low voltage integrated circuits.
dc.title A novel 16x64 2R-1W low power register-file with a stacked SRAM leakage suppression scheme - by Nadida Ghassan Raad.
dc.type Thesis
dc.contributor.department American University of Beirut. Faculty of Engineering and Architecture. Department of Electrical and Computer Engineering.


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