New out-of-order algorithms for future energy efficient cores

Abstract

With semiconductor advances following Moore's law by fitting twice as many transistors every two years on the same die size, designers continue to increase number of cores and cache size. Parallel applications can take advantage of the additional resources while legacy and modern applications with limited parallelism cannot. Power budgets constrain number of simultaneously active cores preventing some parallel applications from taking advantage of available silicon. Hence, the power wall has been reached and as a result power has become a first class design problem. Multiple simpler cores are believed to be more power-efficient than large power-hungry processors. But multi-core and coarse-grain parallelism alone will not solve the problem. Further improvements in single core design are necessary to avoid transistor under-utilization and excessive energy consumption. This dissertation improves fine-grain parallelism and power efficiency by introducing two novel single core designs. Additionally, coarse-grain parallelism is improved in a novel multi-core architecture designed for future power and performance efficient chip multiprocessors. Power efficiency can be achieved either by improving performance, or throughput in the case of multi-core chips, while maintaining power consumption. This means doing more work in less time without requiring extra energy. Alternatively, power efficiency can be achieved by maintaining performance while reducing power. Aiming for improving power efficiency, this dissertation contributes to microprocessor architecture by introducing three novel designs. First, the Fine-Grain Data Threaded core is an in-order core that can dynamically execute a set of contiguous instructions from a sequential program as two threads of data dependent instructions. This core improves performance of sequential programs by 7percent for about the same power consumption. Second, Virtual Register Renaming core is introduced. This is a check-point architecture that introduces a new algorithm for out-of-order in