dc.contributor.author |
Najjar, Elias Abdallah. |
dc.date.accessioned |
2013-10-02T09:23:57Z |
dc.date.available |
2013-10-02T09:23:57Z |
dc.date.issued |
2013 |
dc.identifier.uri |
http://hdl.handle.net/10938/9671 |
dc.description |
Thesis (M.E.)--American University of Beirut, Department of Electrical and Computer Engineeering, 2013. |
dc.description |
Advisor : Dr. Haitham Akkary, Associate Professor, Electrical and Computer Engineering--Committee Members : Dr. Ayman Kayssi, Professor, Electrical and Computer Engineering ; Dr. Ali Chehab, Associate Professor, Electrical and Computer Engineering. |
dc.description |
Includes bibliographical references (leaves 97-98) |
dc.description.abstract |
Most processors nowadays implement old instruction set architectures. While the designs implement new architectures, they remain binary compatible with all previous versions of the ISA. Hardware manufacturers drive away from building new ISAs because the architecture will lose all software applications that were developed for its predecessors. Porting code for one ISA to another requires significant effort from software engineers. As a result there are mainly two ISAs that dominate the market: the x86 which is well established in the personal computer market, and ARM which targets mobile computing devices. While each of the two standards maintains binary compatibility with its own older versions, x86 and ARM are not compatible with each other. This creates a gap between software and different instruction set architectures. Binary translation plays the role of bridging this gap, allowing cross-ISA compatibility. Using binary translation, code compiled for one ISA can be made to run on hardware that implements a completely different ISA. This thesis addresses the problem of binary compatibility by the use of binary translation. There are two ways binary translation can be implemented: either at the software layer, or at the hardware layer. Most of the research that has been done has focused on software approaches. Alternatively, this work aims at implementing the translation completely in hardware, thus gaining the advantages of lower level optimizations and higher execution speeds. We investigated whether it is possible to build an x86 to ARM binary interpreter without modifying the ARM instruction set architecture. This thesis covers the design and implementation of the ARM core and the x86 to ARM interpreter that is responsible for translating the x86 instructions into one or more ARM instructions. The resulting platform was able to handle all kinds of x86 instructions, including those that use 8 and 16 bit registers which the ARM processor does not support. This enables the use of the interpreter with any AR |
dc.format.extent |
xv, 98 leaves : ill. (some col.) ; 30 cm. |
dc.language.iso |
eng |
dc.relation.ispartof |
Theses, Dissertations, and Projects |
dc.subject.classification |
ET:005833 AUBNO |
dc.subject.lcsh |
Computer architecture. |
dc.subject.lcsh |
Hardware. |
dc.subject.lcsh |
Mobile computing. |
dc.subject.lcsh |
Computer engineering. |
dc.subject.lcsh |
RISC microprocessors. |
dc.subject.lcsh |
Systems on a chip. |
dc.subject.lcsh |
Microprocessors. |
dc.title |
Design and implementation of an X86 to ARM hardware binary translator |
dc.type |
Thesis |
dc.contributor.department |
American University of Beirut. Faculty of Engineering and Architecture. Department of Electrical and Computer Engineering. |