This thesis describes the architecture of a dynamically reconfigurable, multi-po rted register file for soft processor cores. The register file is designed using block RAMs found in high-density FPGAs like the Xilinx Virtex-4. The latency of the register
Description:
Thesis (M.E.)--American University of Beirut, Dept. of Electrical and Computer Engineering, 2008.;"Advisor : Dr. Mazen Saghir, Assistant Professor , Department of Electrical and Computer Engineering--Member of Committee : Dr. Ayman Kayssi, Professor , Dep
